Density enhancement of a neural network using FPGAs and run-time reconfiguration
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 4, 180-188
- https://doi.org/10.1109/fpga.1994.315611
Abstract
Run-time reconfiguration is a way of more fully exploitingthe flexibility of reconfigurable FPGAs. The Run-TimeReconfiguration Artificial Neural Network (RRANN)uses run-time reconfiguration to increase the hardwaredensity of FPGAs. The RRANN architecture also allowslarge amounts of parallelism to be used and is veryscalable. RRANN divides the backpropagation algorithminto three sequentially executed stages and configures theFPGAs to execute only one stage at a time. The FPGAsare...Keywords
This publication has 3 references indexed in Scilit:
- A VLSI architecture for high-performance, low-cost, on-chip learningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Neural network simulation on a massively parallel cellular array processor: AAP-2Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Parallel Distributed ProcessingPublished by MIT Press ,1986