Effective buffer insertion of clock tree for high-speed VLSI circuits
- 1 July 1992
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 23 (4) , 291-300
- https://doi.org/10.1016/0026-2692(92)90026-w
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Optimum buffer circuits for driving long uniform linesIEEE Journal of Solid-State Circuits, 1991
- Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSIIEEE Journal of Solid-State Circuits, 1986
- Optimal interconnection circuits for VLSIIEEE Transactions on Electron Devices, 1985
- Asynchronous and Clocked Control Structures for VSLI Based Interconnection NetworksIEEE Transactions on Computers, 1983