CMOS customer implementation of the SPARC architecture
- 1 January 1988
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point unit, and a generic coprocessor.<>Keywords
This publication has 3 references indexed in Scilit:
- The scalable processor architecture (SPARC)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- CMOS gate array implementation of the SPARC architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Optimizing compilers for the SPARC architecture-an overviewPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988