DC analysis of current mode logic
- 1 March 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Circuits and Devices Magazine
- Vol. 5 (2) , 21-35
- https://doi.org/10.1109/101.19320
Abstract
A closed-form solution to finding the optimum signal swing for CML (current-mode logic) is illustrated, based on a few parameters of the minimum geometry transistor in a given technology. A simplified transistor model is used to develop the concept of noise margin optimized for both transistor and circuit parameters. It is shown that the voltage swing of the CML gate is not an arbitrary choice for the circuit designer but is deterministic. The effects of gate fan-in and series gating are then included as part of the closed-form solution, yielding an optimized set of parameters for defining all logic functions. Calculation of the maximum fan-out as well as bias regulators and calculation of the voltage drops in the power buses of chip layouts are treated. The procedure described has been used to develop a CML cell library for producing high-performance interface and networking circuits.Keywords
This publication has 6 references indexed in Scilit:
- A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocellIEEE Journal of Solid-State Circuits, 1987
- Bipolar trendsProceedings of the IEEE, 1986
- Worst-case static noise margin criteria for logic circuits and their mathematical equivalenceIEEE Journal of Solid-State Circuits, 1983
- Analytic approximations for propagation delays in current-mode switching circuits including collector-base capacitancesIEEE Journal of Solid-State Circuits, 1981
- A 400 ps bipolar 18 bit RALU using advanced PSAIEEE Journal of Solid-State Circuits, 1980
- Propagation delay in current-mode switching circuitsIEEE Journal of Solid-State Circuits, 1975