A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
- 1 May 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (5) , 807-811
- https://doi.org/10.1109/4.668997
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Half-Swing Clocking Scheme for 75% Power Saving in Clocking CircuitryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- 200 MHz video compression macrocells using low-swing differential logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessorIEEE Journal of Solid-State Circuits, 1996
- A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop schemeIEEE Journal of Solid-State Circuits, 1994