Improvement of latchup hardness by geometry and technology tuning
- 1 October 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 35 (10) , 1609-1615
- https://doi.org/10.1109/16.7361
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Latchup in CMOS TechnologyPublished by Springer Nature ,1986
- Surface induced latchup in VLSI CMOS circuitsIEEE Transactions on Electron Devices, 1984
- DC holding and dynamic triggering characteristics of bulk CMOS latchupIEEE Transactions on Electron Devices, 1983
- Latchup prevention using an N-well epi-CMOS processIEEE Transactions on Electron Devices, 1983
- Comparison of latch-up in p- and n-well CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A review of some charge transport properties of siliconSolid-State Electronics, 1977
- High injection in epitaxial transistorsIEEE Transactions on Electron Devices, 1969