Latchup prevention using an N-well epi-CMOS process
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 30 (10) , 1403-1405
- https://doi.org/10.1109/t-ed.1983.21308
Abstract
A n-well epi-CMOS structure is described to reduce the latchup sensitivity of CMOS. Results demonstrate excellent latchup reduction.Keywords
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