Built-in testing of integrated circuit wafers
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 39 (2) , 195-205
- https://doi.org/10.1109/12.45205
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Probability models for pseudorandom test sequencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Sift-Out Modular RedundancyIEEE Transactions on Computers, 1978
- A Highly Efficient Redundancy Scheme: Self-Purging RedundancyIEEE Transactions on Computers, 1976
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976