SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 631-634
- https://doi.org/10.1109/iedm.1995.499299
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- An AC conductance technique for measuring self-heating in SOI MOSFET'sIEEE Electron Device Letters, 1995
- Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistanceIEEE Electron Device Letters, 1994
- An analytical back-gate bias effect model for ultrathin SOI CMOS devicesIEEE Transactions on Electron Devices, 1993
- Current-drive enhancement limited by carrier velocity saturation in deep-submicrometer fully depleted SOI MOSFETsIEEE Transactions on Electron Devices, 1993