Hardware approaches to cache coherence in shared-memory multiprocessors. 2
- 1 December 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 14 (6) , 61-66
- https://doi.org/10.1109/40.331392
Abstract
Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors.Keywords
This publication has 53 references indexed in Scilit:
- Cooperative shared memoryACM Transactions on Computer Systems, 1993
- Design of an adaptive cache coherence protocol for large scale multiprocessorsIEEE Transactions on Parallel and Distributed Systems, 1992
- Design and analysis of a scalable cache coherence scheme based on clocks and timestampsIEEE Transactions on Parallel and Distributed Systems, 1992
- Two economical directory schemes for large-scale cache coherent multiprocessorsACM SIGARCH Computer Architecture News, 1991
- A snooping cache coherency protocol for hierarchically organized multiprocessorsMicroprocessing and Microprogramming, 1991
- A new solution of coherence protocol for tightly coupled multiprocessor systemsMicroprocessing and Microprogramming, 1990
- Firefly: a multiprocessor workstationIEEE Transactions on Computers, 1988
- Cache coherence protocols: evaluation using a multiprocessor simulation modelACM Transactions on Computer Systems, 1986
- Multiprocessor cache synchronization: issues, innovations, evolutionACM SIGARCH Computer Architecture News, 1986
- Implementing a cache consistency protocolACM SIGARCH Computer Architecture News, 1985