Decomposing the proof of correctness of pipelined microprocessors

This publication has 9 references indexed in Scilit:

• Efficient validity checking for processor verification
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Trace table based approach for pipelined microprocessor verification
  Published by Springer Nature ,1997
• Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods
  Formal Methods in System Design, 1996
• Validity checking for combinations of theories with equality
  Published by Springer Nature ,1996
• Inverting the abstraction mapping: A methodology for hardware verification
  Published by Springer Nature ,1996
• Techniques for verifying superscalar microprocessors
  Published by Association for Computing Machinery (ACM) ,1996
• A scalable formal verification methodology for pipelined microprocessors
  Published by Association for Computing Machinery (ACM) ,1996
• Formal verification for fault-tolerant architectures: prolegomena to the design of PVS
  IEEE Transactions on Software Engineering, 1995
• Automatic verification of pipelined microprocessor control
  Published by Springer Nature ,1994