Wafer Scale Interconnections for GaAs Packaging-Applications to RISC Architecture
- 1 April 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 20 (4) , 21-35
- https://doi.org/10.1109/mc.1987.1663533
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Interconnection lengths and VLSIIEEE Circuits and Devices Magazine, 1985
- Analysis of Interconnection Delay on Very High-Speed LSI/VLSI Chips Using an MIS Microstrip Line ModelIEEE Transactions on Microwave Theory and Techniques, 1984
- Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSIProceedings of the IEEE, 1984
- Optimal interconnect circuits for VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- The trials of wafer-scale integration: Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it flyIEEE Spectrum, 1984
- Thermal Conduction Module: A High-Performance Multilayer Ceramic PackageIBM Journal of Research and Development, 1982
- A Silicon and Aluminum Dynamic Memory TechnologyIBM Journal of Research and Development, 1980
- Placement and average interconnection lengths of computer logicIEEE Transactions on Circuits and Systems, 1979
- On a Pin Versus Block Relationship For Partitions of Logic GraphsIEEE Transactions on Computers, 1971
- Technological foundations and future directions of large-scale integrated electronicsPublished by Association for Computing Machinery (ACM) ,1966