SIESTA: a multi-facet scan design system
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The scan design methodology has led to a mnge of design-for-testability techniques that essentially reduce the problem of test pattern generation (TPG) for sequential circuits to that of combinational TPG. However scan techniques are not universally accepted by circuit designers because of the various overheada involved such as chip area, performance, 1/0 pin count and test application time. This paper presents a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy a designer’s goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues o,f partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems.Keywords
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