A partial scan method for sequential circuits with feedback
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 39 (4) , 544-548
- https://doi.org/10.1109/12.54847
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Concurrent test generation and design for testabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testability analysis of synchronous sequential circuits based on structural dataPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The BACK algorithm for sequential test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Designing circuits with partial scanIEEE Design & Test of Computers, 1988
- A novel clocking technique for VLSI circuit testabilityIEEE Journal of Solid-State Circuits, 1984