A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 696-704
- https://doi.org/10.1109/test.1992.527891
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- TWO FAULT INJECTION TECHNIQUES FOR TEST OF FAULT HANDLING MECHANISMSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Evaluation of error detection schemes using fault injection by heavy-ion radiationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fault injection for dependability validation: a methodology and some applicationsIEEE Transactions on Software Engineering, 1990
- Processor Control Flow Monitoring Using Signatured Instruction StreamsIEEE Transactions on Computers, 1987
- An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program FlowIEEE Transactions on Nuclear Science, 1984