Approaching a nanosecond: a 32 bit adder
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- A 3.1ns 32b Cmos Adder In Multiple Output Domino LogicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Design and fabrication of depletion GaAs LSI high-speed 32-bit adderIEEE Journal of Solid-State Circuits, 1983
- High-Speed Binary AdderIBM Journal of Research and Development, 1981
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960
- A One-Microsecond Adder Using One-Megacycle CircuitryIEEE Transactions on Electronic Computers, 1956