Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems

This publication has 8 references indexed in Scilit:

• A 50-MHz CMOS geometrical mapping processor
  IEEE Transactions on Circuits and Systems, 1989
• High-performance multiple-valued radix-2 signed-digit multiplier and its application
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
• A multiplier chip with multiple-valued bidirectional current-mode logic circuits
  Computer, 1988
• A 32*32-bit multiplier using multiple-valued MOS current-mode circuits
  IEEE Journal of Solid-State Circuits, 1988
• A 33 Mflops Floating Point Processor Using Redundant Binary Representation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
• High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
  IEEE Transactions on Computers, 1985
• A Proof of the Modified Booth's Algorithm for Multiplication
  IEEE Transactions on Computers, 1975
• Signed-Digit Numbe Representations for Fast Parallel Arithmetic
  IEEE Transactions on Electronic Computers, 1961