ESD-related process effects in mixed-voltage sub-0.5 μm technologies

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Abstract
In this paper, we have studied the effect of the process changes that have arisen due to the transition from 0.5 /spl mu/m to 0.18 /spl mu/m gate length on the ESD performance of three generations of CMOS technologies. The current gain (/spl beta/), avalanche multiplication factor (M/sub av/) and effective substrate resistance (R/sub sub/) of the parasitic lateral NPN (LNPN) formed by an nMOS have been shown to be related to the performance of the LNPN under ESD conditions. The effect of processing changes on these 3 parameters along with variations in the injection induced breakdown voltage (BV/sub ii/) of the transistor have been evaluated. It is shown that the reduction in the second breakdown current, I/sub t2/, can be attributed to either a reduction in R/sub sub/, a decrease in /spl beta/, a decrease in M/sub av/ or a combination of these changes. Based on these results, a process monitor for ESD performance is proposed. This paper also characterizes the effect of sub-0.5 /spl mu/m dual-gate-oxide processing on ESD performance and identifies the key process variations affecting ESD performance in mixed voltage technologies.

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