Polycrystalline-silicon device technology for large-area electronics

Abstract
The process sequence used to fabricate post-hydrogenated polycrystalline silicon thin-film devices has a dramatic impact on performance. A near-optimal process for devices that have hole mobilities of up to 50 cm2/V . s and electron mobilities of 70 cm2/V . s is demonstrated. These observed mobilities are substantially higher than previous literature reports. Implantation of boron or phosphorus into the polycrystalline-silicon device channel after the gate-oxidation step allows threshold-voltage tailoring for achievement of either enhancement-or depletion-mode operation of n- and p-channel devices. These results indicate that CMOS or NMOS logic could be fabricated using polycrystalline-silicon devices. Devices with steam-grown gate oxides have reduced channel mobility in comparison with devices oxidized in dry O2at the same temperature. Possible mechanisms for the variation in performance with oxidation conditions are discussed.