Redundancy identification and removal based on implicit state enumeration
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- Redundancies and don't cares in sequential logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- New ATPG techniques for logic optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test generation for highly sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The use of observability and external don't cares for the simplification of multi-level networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Implicit state enumeration of finite state machines using BDD'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Don't care minimization of multi-level sequential logic networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The transduction method-design of logic networks based on permissible functionsIEEE Transactions on Computers, 1989
- Test generation for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- A Nand Model ror Fault Diagnosis in Combinational Logic NetworksIEEE Transactions on Computers, 1971