Processor-based built-in self-test for embedded DRAM
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (11) , 1731-1740
- https://doi.org/10.1109/4.726568
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
- A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BISTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- Computational Ram: A Memory-simd Hybrid And Its Application To DspPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Custom ASIC VLSI device for asynchronous transfer modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 μm logic processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A multimedia 32 b RISC microprocessor with 16 Mb DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An ASIC library granular DRAM macro with built-in self testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 370-MHz memory built-in self-test state machinePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.6 GB/s data-transfer-rate 8 Mb embedded DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A Pixel-parallel Image Processor Using Logic Pitch-matched To Dynamic MemoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Test generation for VLSI chips with embedded memoriesIBM Journal of Research and Development, 1990