A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST
- 1 September 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An embedded DRAM macro fabricated in 65nm CMOS achieves 1.0GHz multi-banked operation at 1.0V yielding 584 Gbits/sec. The array utilizes a 0.11μm 2 cell with 20fF deep trench capacitor and 2.2nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333MHz at 1.0V with functional operation from 750mV to 1.5V and densities up to 36.5Mbits.Keywords
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