Design of signature circuits based on weight distributions of error-correcting codes
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 779-785
- https://doi.org/10.1109/test.1990.114095
Abstract
Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2/sup m/). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105.Keywords
This publication has 12 references indexed in Scilit:
- Aliasing in signature analysis testing with multiple-input shift-registersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Arithmetic and galois checksumsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Aliasing errors in multiple input signature analysis registersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An iterative technique for calculating aliasing probability of linear feedback signature registersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Aliasing probability for multiple input signature analyzerIEEE Transactions on Computers, 1990
- An analysis of the aliasing probability of multiple-input signature registers in the case of a 2/sup m/-ary symmetric channelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Analysis and proposal of signature circuits for LSI testingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Bounds and analysis of aliasing errors in linear feedback shift registersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Built-In Self-Test TechniquesIEEE Design & Test of Computers, 1985
- Built-in test for complex digital integrated circuitsIEEE Journal of Solid-State Circuits, 1980