Parallel implementations of discrete relaxation technique on fixed size processor arrays
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 184-198
- https://doi.org/10.1109/asap.1991.238884
Abstract
Discrete relaxation technique has been widely used in pattern recognition, artificial intelligence and computer vision. For the consistent labeling problem for labeling n objects with m labels, a parallel implementation based on a new sequential algorithm is shown. This non-partitioned parallel implementation runs in O(nm) time using nm PE's. Two partitioned implementations are then proposed. In the first implementation, O(n/sup 2/m/sup 2//P) time performance is achieved by using P PE's connected to a common bus, where Por=P/sup 2/.Keywords
This publication has 9 references indexed in Scilit:
- Parallel algorithms and architectures for discrete relaxation techniquePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An optimal lookahead processor to prune search spacePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Polymorphic-torus networkIEEE Transactions on Computers, 1989
- The Gated Interconnection Network for Dynamic ProgrammingPublished by Springer Nature ,1988
- A Parallel Architecture for Discrete Relaxation AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Parallel consistent labeling algorithmsInternational Journal of Parallel Programming, 1987
- Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling ProblemIEEE Transactions on Computers, 1985
- Matching Images Using Linear FeaturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Scene Labeling by Relaxation OperationsIEEE Transactions on Systems, Man, and Cybernetics, 1976