Implementation of CMP-based design rules and patterning practices

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Abstract
This paper discusses specific die patterning techniques utilized during the implementation of a CMP-based BEOL within Digital's Alpha technologies. Customary application of inter-level dielectric (ILD) CMP, to eliminate topographically induced defect mechanisms and increase photolithographic focal budget margins for Alpha, indicated the need to strictly control both interand intra-die dielectric capacitance and thickness. To this end, several die patterning strategies were used to minimize the feature size and pattern density dependencies of ILD CMP as well as aid in the fast paced evolution from test vehicle to product chip reticles. Quantification of inter-level and intra-die thickness control with respect to ghost/partial die patterning, zero level (ZL) and perimeter bordering, dummy/filler feature patterning and general CMP-based design rules will be addressed within the context of analysis of variance (ANOVA). Further discussed will be the empirical rules-of-thumb and critical dimension (CD) variance definitions which provided the planarity targets utilized throughout the framework of these experiments.

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