Simultaneous switching ground noise calculation for packaged CMOS devices
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11) , 1724-1728
- https://doi.org/10.1109/4.98995
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Negative feedback influence on simultaneous switching CMOS outputsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Effects of skewing CMOS output driver switching on the 'simultaneous' switching noisePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Effect of device and interconnect scaling on the performance and noise of packaged CMOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Computation of transients in lossy VLSI packaging interconnectionsIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1990
- Delta-I noise specification for a high-performance computing machineProceedings of the IEEE, 1985
- Computing Inductive Noise of Chip PackagesAT&T Bell Laboratories Technical Journal, 1984