An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs
- 1 July 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 46 (7) , 1378-1383
- https://doi.org/10.1109/16.772479
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Tenth micron p-MOSFET's with ultra-thin epitaxial channel layer grown by ultra-high-vacuum CVDPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-performance double-layer epitaxial-channel PMOSFET compatible with a single gate CMOSFETPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design methodology for low-voltage MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Kinetics of arsenic doping in silicon by ultra-high-vacuum chemical vapor depositionJournal of Crystal Growth, 1995
- Scanning tunneling microscopy observation of hydrogen-terminated Si(111) surfaces at room temperatureApplied Physics Letters, 1994
- Scaling the MOS transistor below 0.1 μm: methodology, device structures, and technology requirementsIEEE Transactions on Electron Devices, 1994
- A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFETPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Deep-submicrometer MOS device fabrication using a photoresist-ashing techniqueIEEE Electron Device Letters, 1988