Computing Architectural Vulnerability Factors for Address-Based Structures
Top Cited Papers
- 28 July 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 532-543
- https://doi.org/10.1109/isca.2005.18
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic InstrumentationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The Soft Error Problem: An Architectural PerspectivePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Techniques to Reduce the Soft Error Rate of a High-Performance MicroprocessorACM SIGARCH Computer Architecture News, 2004
- Automatically characterizing large scale program behaviorPublished by Association for Computing Machinery (ACM) ,2002
- Asim: a performance model frameworkComputer, 2002
- Dead-block prediction & dead-block correlating prefetchersPublished by Association for Computing Machinery (ACM) ,2001
- A model for estimating trace-sample miss ratiosPublished by Association for Computing Machinery (ACM) ,1991