Mismatch characterization of small size MOS transistors
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.Keywords
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