SMART (strategic memory allocation for real-time) cache design using the MIPS R3000
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 9, 322-330
- https://doi.org/10.1109/real.1990.128764
Abstract
SMART, a technique for providing predictable cache performance for real-time systems with priority-based preemptive scheduling, is presented. The technique is implemented in a R3000 cache design. The value density acceleration (VDA) cache allocation algorithm is also introduced, and shown to be suitable for run-time cache allocation.Keywords
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