A new CR-delay circuit technology for high-density and high-speed DRAMs
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 905-910
- https://doi.org/10.1109/4.34069
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structureIEEE Journal of Solid-State Circuits, 1988
- A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rateIEEE Journal of Solid-State Circuits, 1988
- A new CR-delay circuit technology for high-density and high-speed DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A 60-ns 4-Mbit CMOS DRAM with built-in selftest functionIEEE Journal of Solid-State Circuits, 1987
- A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifierIEEE Journal of Solid-State Circuits, 1987
- A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifierIEEE Journal of Solid-State Circuits, 1986