Dynamic frequency and voltage control for a multiple clock domain microarchitecture
- 26 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scalingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Power and performance evaluation of globally asynchronous locally synchronous processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Low-latency asynchronous FIFO's using token ringsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low-latency FIFO for mixed-clock systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Power-Efficient Issue Queue DesignPublished by Springer Nature ,2002
- Real-time dynamic voltage scaling for low-power embedded operating systemsPublished by Association for Computing Machinery (ACM) ,2001
- Active GHz clock network using distributed PLLsIEEE Journal of Solid-State Circuits, 2000
- Clocking design and analysis for a 600-MHz Alpha microprocessorIEEE Journal of Solid-State Circuits, 1998
- Will physical scalability sabotage performance gains?Computer, 1997
- Comparing algorithm for dynamic speed-setting of a low-power CPUPublished by Association for Computing Machinery (ACM) ,1995