A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems
- 1 April 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 26 (4) , 390-396
- https://doi.org/10.1109/t-ed.1979.19440
Abstract
A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV-2. The bipolar transistors have a low-resistance base contact. Current gain βFcan be set independently. For\beta_{F} = 90, the Early voltage isV_{A} = 110V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.Keywords
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