A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 370-371,
- https://doi.org/10.1109/isscc.1996.488721
Abstract
Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.Keywords
This publication has 2 references indexed in Scilit:
- A 100-MHz 4-Mb cache DRAM with fast copy-back schemeIEEE Journal of Solid-State Circuits, 1992
- A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECCIEEE Journal of Solid-State Circuits, 1990