An excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks

Publisher Website

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1993.347283

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

A functional MOS transistor featuring gate-level weighted sum and threshold operations
IEEE Transactions on Electron Devices, 1992
Characteristics of floating gate device as analogue memory for neural networks
Electronics Letters, 1991
Optimum design of dual-control gate cell for high-density EEPROM's
IEEE Transactions on Electron Devices, 1985