A functional MOS transistor featuring gate-level weighted sum and threshold operations
- 1 June 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 39 (6) , 1444-1455
- https://doi.org/10.1109/16.137325
Abstract
A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the 'on' and 'off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed.<>Keywords
This publication has 17 references indexed in Scilit:
- A self-learning neural-network LSI using neuron MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An intelligent MOS transistor featuring gate-level weighted sum and threshold operationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A multiple valued logic: a tutorial and appreciationComputer, 1988
- Comparison of binary and multivalued ICs according to VLSI criteriaComputer, 1988
- A multiplier chip with multiple-valued bidirectional current-mode logic circuitsComputer, 1988
- Design of a highly parallel AI processor using new multiple-valued MOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Design and implementation of quaternary NMOS integrated circuits for pipelined image processingIEEE Journal of Solid-State Circuits, 1987
- An optimally designed process for submicrometer MOSFET'sIEEE Transactions on Electron Devices, 1982
- The Prospects for Multivalued Logic: A Technology and Applications ViewIEEE Transactions on Computers, 1981
- A logical calculus of the ideas immanent in nervous activityBulletin of Mathematical Biology, 1943