Experience in functional-level test generation and fault coverage in a silicon compiler

4 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 485-490
https://doi.org/10.1109/edac.1990.136696

Abstract

During the design cycle of VLSI circuits, test vector generation is often a very time consuming and costly step.Many strategies concerning automatic test pattern generation have been published. Usually they are restrictive and consider the circuit as an undifferentiated mass of gates while ignoring the hierarchy used during the design process. The test vectors so generated are based on the traditional stuck-at-fault model.In this paper, an ATPG methodology is presented which is based on "functional testing" of each block logic and not on testing each gate or net. The methodology is not limited to combinatorial logic or scan-path designs, and here, is applied to datapath circuits composed of functional blocks (such as ALU, etc) and to state machines.

Keywords

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