1 K*128 high-performance, low power configurable CMOS SRAM compiler
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. P3/5.1-P3/5.4
- https://doi.org/10.1109/asic.1990.186108
Abstract
A high-density, high-performance, low-power, configurable, fully static RAM compiler is discussed. The compiler can generate different SRAM configurations with a minimum of 128 bits, up to a maximum of 128 K bits. The SRAM has been verified in silicon to have a typical access time of 11 ns (1.0- mu m ASIC process) for a 4 K*16 configuration and is functional from 3.5 V to 7.0 V power supply.Keywords
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