High performance CMOS dual-port SRAM compiler
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 32, P3-2/1
- https://doi.org/10.1109/asic.1989.123185
Abstract
A high-density, high-performance dual-port SRAM (static RAM) compiler has been developed with standard product features. The compiler can generate different SRAM configurations with a minimum of 512 bits up to a maximum of 9 kbits. The SRAM has a typical access time of 15 ns (1.5- mu m ASIC (application-specific integrated circuit) process) for the largest configuration (1 K words*9 bits or 512 words*18 bits). It is scalable to a 1- mu m ASIC process with a typical access time of 9 ns. The compiler takes only five min to generate a complete layout block, a transistor netlist, or a gate-level model netlist for any SRAM configuration.< >Keywords
This publication has 4 references indexed in Scilit:
- A new language suite for designer-specifiable ASIC cell compilersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 256K CMOS SRAM with variable impedance data-line loadsIEEE Journal of Solid-State Circuits, 1985
- A fast 8K × 8 mixed CMOS static RAMIEEE Transactions on Electron Devices, 1985
- A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAMIEEE Journal of Solid-State Circuits, 1981