Efficient timing analysis algorithms for timed state space exploration
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Algorithms for interface timing verificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Specification and analysis of timing constraints in signal transition graphsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A fully-asynchronous low-power error corrector for the DCC player [CMOS technology]Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Bounded delay timing analysis of a class of CSP programs with choicePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automatic synthesis of gate-level timed circuits with choicePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 100-MIPS GaAs asynchronous microprocessorIEEE Design & Test of Computers, 1994
- The Post Office experience: designing a large asynchronous chipIntegration, 1993
- Synthesis of timed asynchronous circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
- What good are digital clocks?Published by Springer Nature ,1992
- Modeling and verification of time dependent systems using time Petri netsIEEE Transactions on Software Engineering, 1991