Nanocrystalline silicon thin film transistors

Publisher Website
Google Scholar
Abstract
P-channel and n-channel thin film transistors (TFTs) can be made from directly deposited nanocrystalline silicon (nc-Si:H) at temperatures as low as 150°C. A staggered top gate, bottom source/drain geometry, which is adapted to the structural evolution of nc-Si:H, ensures that the channel is the last-to-grow layer, avoids plasma etch damage, and opens a wide process window for source/drain patterning. The TFT structure is fabricated on top of a ∼50 nm thick intrinsic nc-Si:H seed layer, which serves to develop the crystalline structure of the channel layer. A hole mobility of ∼0.2 cm2 V−1 s−1 and an electron mobility of ∼40 cm2 V−1 s−1 are obtained in TFTs on glass substrates, at a maximum process temperature of 150°C. The processes have been integrated for p- and n-channel TFT fabrication on single glass or Kapton E polyimide substrates. The p-channel TFTs reach a hole mobility of ∼0.2 cm2 V−1 s−1 on glass and ∼0.17 cm2 V−1 s−1 on Kapton, and the n-channel TFTs have an electron mobility of ∼30 cm2 V−1 s−1 on glass and ∼23 cm2 V−1 s−1 on Kapton. These mobility values suggest that directly deposited nc-Si:H is an attractive channel material for realising CMOS on plastic. However, high gate leakage and shifts in the TFT characteristics indicate that the gate dielectric and the channel layer/dielectric interface are not yet ready for CMOS fabrication.