Concurrent error detection in highly structured logic arrays
- 1 August 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (4) , 583-594
- https://doi.org/10.1109/jssc.1987.1052776
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Strongly code disjoint checkersIEEE Transactions on Computers, 1988
- Designing for concurrent error detection in VLSI: application to a microprogram control unitIEEE Journal of Solid-State Circuits, 1987
- On Separable Unordered CodesIEEE Transactions on Computers, 1984
- PLA Implementation of k-out-of-n Code TSC CheckerIEEE Transactions on Computers, 1984
- Concurrent Error Detection and Testing for Large PLA'sIEEE Journal of Solid-State Circuits, 1982
- An Improvement of Reliability of Memory System with Skewing ReconfigurationIEEE Transactions on Computers, 1981
- Strongly Fault Secure Logic NetworksIEEE Transactions on Computers, 1978
- Efficient Algorithms for Testing Semiconductor Random-Access MemoriesIEEE Transactions on Computers, 1978
- On Totally Self-Checking Checkers for Separable CodesIEEE Transactions on Computers, 1977
- A note on error detection codes for asymmetric channelsInformation and Control, 1961