Microarchitecture of HaL's cache subsystem
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10636390,p. 267-271
- https://doi.org/10.1109/cmpcon.1995.512395
Abstract
HaL's cache subsystem is designed to provide high memory bandwidth to the processor. The cache is non-blocking: the cache can service a new CPU request while four cache line refills are progressing in the background. The cache subsystem is also designed to handle speculative and out-of-order CPU requests. The cache-CPU interface protocol allows precise interrupts to be maintained under out-of-order completion. The cache design, as other parts in HaL's PM1 module pays attention to reliability and availability (RAS). The design takes advantage of SPARC V9's RED state feature, and allows the software to recover from certain hardware errors. In addition, the cache uses SECDED (Single Error Correction Double Error Detection) to protect its data store and parity to protect its tag store.Keywords
This publication has 3 references indexed in Scilit:
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- Architectural overview of HaL systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002