Microarchitecture of HaL's CPU
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.Keywords
This publication has 7 references indexed in Scilit:
- A 14-port 3.8 ns 116-word 64b read-renaming register filePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 64b 4-issue out-of-order execution RISC processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Microarchitecture of HaL's cache subsystemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Microarchitecture of HaL's memory management unitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Architectural overview of HaL systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A zero-overhead self-timed 160-ns 54-b CMOS dividerIEEE Journal of Solid-State Circuits, 1991
- Checkpoint Repair for High-Performance Out-of-Order Execution MachinesIEEE Transactions on Computers, 1987