A novel macromodel for power estimation in CMOS structures

This publication has 16 references indexed in Scilit:

• Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Design and selection of buffers for minimum power-delay product
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Explicit evaluation of short circuit power dissipation for CMOS logic structures
  Published by Association for Computing Machinery (ACM) ,1995
• Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay
  IEEE Journal of Solid-State Circuits, 1994
• Power efficient technology decomposition and mapping under an extended power consumption model
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
• Short-circuit power dissipation estimation for CMOS logic gates
  IEEE Transactions on Circuits and Systems I: Regular Papers, 1994
• Input waveform slope effects in CMOS delays
  IEEE Journal of Solid-State Circuits, 1990
• Explicit formulation of delays in CMOS data paths
  IEEE Journal of Solid-State Circuits, 1988
• Accurate simulation of power dissipation in VLSI circuits
  IEEE Journal of Solid-State Circuits, 1986
• Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
  IEEE Journal of Solid-State Circuits, 1984