A 5-Bit Building Block for 20 MHz NMOS A/D Converters
- 1 September 1980
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.Keywords
This publication has 2 references indexed in Scilit:
- A high-speed 7 bit A/D converterIEEE Journal of Solid-State Circuits, 1979
- Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converterIEEE Journal of Solid-State Circuits, 1979