Thin gate oxide behavior during plasma patterning of silicon gates
- 23 August 1999
- journal article
- conference paper
- Published by AIP Publishing in Applied Physics Letters
- Vol. 75 (8) , 1069-1070
- https://doi.org/10.1063/1.124599
Abstract
We have evidenced an unexpected behavior of thin gate oxide layers (thickness in the range 2–4 nm) exposed to plasma processes developed for the patterning of 0.1 μm silicon gates. During the low-energy overetch step of the process, an oxidation of the bulk underlying silicon takes place, leading to the growth of the gate oxide layer. Experimental results obtained from in situ kinetic and spectroscopic ellipsometry measurements and supported by x-ray photoelectron spectroscopy analyses are presented to highlight this phenomenon.Keywords
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