A design methodology of bipolar standard cell LSIs for Gbit/s signal processing
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A bipolar standard cell LSI design methodology for Gbit/s LSIs is described. A unique configuration of cell libraries which have internal fixed routing channels especially for differential clocks and a clock distribution scheme that considers the equal length and load of differential clocks makes it possible to achieve a 1.8 Gbit/s 2.5 K-gate LSI.Keywords
This publication has 2 references indexed in Scilit:
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- 43-ps 5.2-GHz macrocell array LSIsIEEE Journal of Solid-State Circuits, 1988