A 50 µ A standby 1MW × 1b/256KW × 4b CMOS DRAM

1 January 1986

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXIX, 266-267
https://doi.org/10.1109/isscc.1986.1156942

Abstract

A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half Vcccc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well measuring 3.24μm²has resulted in a chip size of 4.4×12.3mm²with an access time of 56ns.

Keywords

RANDOM ACCESS MEMORY
READ-WRITE MEMORY
VOLTAGE
CAPACITANCE
TESTING
FLIP-FLOPS
DRIVER CIRCUITS
CMOS TECHNOLOGY
BORON
IMPLANTS

This publication has 2 references indexed in Scilit:

A reliable 1-Mbit DRAM with a multi-bit-test mode
IEEE Journal of Solid-State Circuits, 1985
A 1-Mbit CMOS DRAM with fast page mode and static column mode
IEEE Journal of Solid-State Circuits, 1985