A global wiring paradigm for deep submicron design
- 1 January 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 19 (2) , 242-252
- https://doi.org/10.1109/43.828553
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Global wires: harmful?Published by Association for Computing Machinery (ACM) ,1998
- Figures of merit to characterize the importance of on-chip inductancePublished by Association for Computing Machinery (ACM) ,1998
- Clocking design and analysis for a 600-MHz Alpha microprocessorIEEE Journal of Solid-State Circuits, 1998
- Package clock distribution design optimization for high-speed and low-power VLSIsIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1997
- 200-MHz superscalar RISC microprocessorIEEE Journal of Solid-State Circuits, 1996
- Performance trends in high-end processorsProceedings of the IEEE, 1995
- Time-domain macromodels for VLSI interconnect analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIsIEEE Transactions on Electron Devices, 1993
- Placement and average interconnection lengths of computer logicIEEE Transactions on Circuits and Systems, 1979